The present invention relates to integrated circuits and, more particularly, to integrated circuits with conductive lines with reduced line pitch.
In integrated circuits, parallel conductive lines are widely used to interconnect circuit elements. FIG. 1 shows parallel conductive lines 120 separated by line spaces 130 on a substrate 101. The width of the line spacing and conductive line is referred to as the xe2x80x9cline pitchxe2x80x9d. A limiting factor to reducing the line pitch is the minimum resolution or feature size (F) of a specific lithographic tool. With the line spacing and line width equal to 1F each, the minimum pitch is 2F.
One technique for reducing line pitch below 2F is to reduce the width of the line spacing between conductive lines. However, reducing the line spacing brings conductive lines together. This results in an increase in the capacitive coupling noise, which can adversely impact the integrity of signals on adjacent conductive lines.
As evidenced from the foregoing discussion, it is desirable to provide conductive lines with less to 2F pitch without increasing the capacitive coupling between adjacent lines.
The invention relates to integrated circuit in general. In one embodiment, the integrated circuit comprises conductive lines having non-rectangular shaped cross-sections. The conductive lines are separated by a line space. In one embodiment, the conductive lines comprise first and second sidewalls. One of the sidewalls is non-vertical. In one embodiment, the angles of the non-vertical sidewalls of the adjacent conductive lines are supplementary angles. In one embodiment, the non-vertical sidewalls of adjacent conductive lines are adjacent. By providing the conductive lines with a non-rectangular shaped cross-section, a reduction in line pitch is achieved without increasing capacitive coupling noise between adjacent lines. Alternatively, for a given pitch, conductive lines with the non-rectangular shaped cross-sections reduce capacitive coupling noise between adjacent lines.